Dynamic random access memory (DRAM) requires regular refreshing of the contents of the memory to prevent data loss. In operation of a memory device, certain refresh cycles are required in order to maintain memory, but further to maintain compliance with memory standards. A system may be authorized to pull in (issue in advance) or postpone a certain number of refresh commands.
In addition to the required refresh commands, a memory device may perform self-refresh cycles in self-refresh mode. However, in operation, a memory controller is required at time to delay entry to self-refresh mode in order to catch up on the required refreshes. This operation can require significant consumption of power for systems in completing refresh cycles, and then proceeding into a self-refresh mode.